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The figure shows a common implementation of a phase frequency detector (PFD), which basically consists of two D-type flip-flops. One Q output enables a positive current source and the other Q output enables a negative current source. Assuming that the D-type flip-flop in this design is triggered by a positive edge, the possible states are as shown in the logic table. 
Figure: Phase Frequency Detector (PFD) Drive Charge Pump (CP)